India Development Center Hyderabad

Job Title: SoC/Chip Design Lead/Manager
Job Title: SoC/Chip Verification Lead/Manager
Job Title: Power Management IC Design Engineer/Senior Design Engineer
Job Title: Veriwave Testing
Job Title: RTL Design Engineer
Job Title: Baseband Design Engineer / Baseband Sr. Design Engineer
Job Title: VLSI Design Engineer
Job Title: VLSI Verification Engineer
Job Title: Bluetooth Developer

Job Title: SoC/Chip Design Lead/Manager

Experience: 6-10 years with at least 2 years as a Lead/Manager
Location: Hyderabad, India
Job Description :

The position requires strong knowledge of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, interconnects, memory architecture and caches, multiple clocks and resets, high-speed interfaces, peripherals. The candidate should be able to contribute to and own multiple development stages like architecture, microarchitecture, verification of SoCs which include ARM Cortex and proprietary processor designs, AMBA AHB/AXI/APB interconnects buses, high-speed interfaces for off-chip memories and be able to deliver reusable and robust IP. The candidate should have knowledge of SoC design flows and signoff criteria including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure. Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) is part of the minimum requirements. The candidate is expected to work closely with the Software/Firmware, Silicon Validation/Characterization and Product Management teams. The candidate is expected to lead a team of engineers and be responsible for project management including preparing project plans and ensuring proper communication of milestones and status during the project.

Minimum Qualifications:
  • Experience of architecting, implementing and verifying complex SoC/chip architectures with multi-core, multi-threaded processor technology, AMBA AHB/AXI/APB bus matrices, multiple clocks and resets and memory and cache architecture.
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
  • Knowledge of DFT including Scan, MBIST
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Knowledge of Verilog and System Verilog
Preferred Qualifications:
  • Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee, GPS
  • Knowledge of System Verilog, UVM, C/C++
  • Leadership and mentoring skills
  • Project and Schedules Management with proper communication of milestones and status at different stages of the project
  • Exceptional problem-solving skills
  • Good written and oral communication skills
Education Requirements:
  • B.Tech/M.Tech in ECE, EEE or CSE

Job Title: SoC/Chip Verification Lead/Manager

Experience: 6-10 years with at least 2 years as a Lead/Manager
Location: Hyderabad, India
Job Description :

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN. The candidate should be able to assist post-silicon validation teams. The candidate is expected to lead a team of engineers and be responsible for project management including planning, tracking and communicating milestones and status during the project to various stakeholders.

Minimum Qualifications:
  • Experience of architecting and developing chip/SoC level testbenches with multiple interfaces with the goal of verifying and signing off power, performance and functionality
  • Develop and signoff on test plans and test cases
  • Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture
  • Should have worked on verification at least one of SDIO, USB, PCIe, Ethernet
  • Strong knowledge of Verilog, System Verilog, UVM, C/C++
  • Experience in usage of assertions, constrained random generation, functional/code coverage.
  • Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows
  • Analytical debugging skills
Preferred Qualifications:
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN
  • Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee, GPS
  • Leadership and mentoring skills
  • Project and Schedules Management with proper communication of milestones and status at different stages of the project
  • Exceptional problem-solving skills
  • Good written and oral communication skills
Education Requirements:
  • B.Tech/M.Tech in ECE, EEE or CSE

Job Title: Power Management IC Design Engineer/Senior Design Engineer

Experience: 2 - 6 Years
Location: Hyderabad, India
Job Description :

Redpine's Power Management group has openings for engineering talent with expertise in PMIC. We are looking for a Power Management IC Design Engineer/Senior Design Engineer with hands on experience in designing ICs for Buck /Boost Regulators, Linear Regulators, Battery Chargers, Energy harvesters and other analog integrated circuits. Candidate will be participating in all phases of product development including product definition, architecture, layout, analog circuit design and lab evaluations and debug. Candidate should have understanding at the product level (chargers, energy harvesting, Power Supplies), as this will help with product definition and provide deeper understanding of the PMIC function.

Requirements:
  • Relevant experience in both linear and switching power supplies including buck and/or boost regulators.
  • Relevant experience in battery charger and energy harvesting circuits
  • Understanding of feedback systems and stability analysis in both time and frequency domains.
  • Solid understanding of design and analysis of transistor-level low-power analog integrated circuits.
  • Proficiency in Cadence Design Environment for Analog, Mixed-Signal and RF designs.
  • Ability to use tools like Excel, Matlab for system level architecture, design and modeling.
  • Team player with ability to drive product development to completion.
  • Good communication skills and experience in technical documentation.
Education Requirements:
  • B.Tech/MS/M.Tech/Ph.D in EE / ECE

Job Title: Veriwave Testing

Experience: 2 - 5 Years
Location: Hyderabad, India
Job Description :
  • Test experience with Ixia Chariot product family IxChariot, IxVeriwave, capability to maintain and test independently
  • Experience with packet tracing/sniffing tools (Wireshark or Omnipeek), RF site survey tools and RF spectrum analyzers
  • Automation experience: capable of scripting (Python, Perl, TCL)
  • In depth understanding of 802.11a/b/g/n/ac WiFi standards and related components especially the access points and WiFi clients/supplicants
  • Working knowledge of Linux based network servers and test tools CCNA/CWNA (or higher) certification is desirable
  • Working knowledge in L2/L3 network protocols including bridging, VLANs, NAT, routing, TCP/IP, DHCP, SSL, HHTP/HTTPS, 802.1X is desirable
  • Working knowledge of basic QoS, VLANs, STP, RSTP Protocols is desirable
  • Quick learner with an excellent interpersonal, verbal/written communications, problem solving and decision-making skills
  • Strong written skills specifically as related to writing test plans and test reports
Education Requirements:
  • B.Tech / M.Tech

Job Title: RTL Design Engineer

Experience: 3 - 6 Years
Location: Hyderabad, India
Job Description :
  • Implement various PHY layer blocks in Verilog (given micro-architecture design).
  • Microarchitecture design tasks will be assigned based on ability, if not candidate will be trained for the same.
  • This position is for Redpine's new chip on 802.11ax and NB-IoT (Rel 13, 14, 15) which are the very latest standards in wireless.
  • Candidate will get a unique opportunity to associate with a world class design with lowest power consumption.
  • He will also have a huge learning opportunity on various design aspects of wireless from industry veterans.
  • A fast track growth opportunity to a team lead is also a possibility.
Desired skills/background:
  • Basic understanding of communications and signal processing
  • Basic understanding of Matlab Implementation
  • Good understanding of Verilog
  • VHDL experience will also be considered.
  • Prior experience in physical layer (digital baseband) is strongly preferred.
  • Micro-architecture experience or understanding is a plus but not required.
  • Candidates who are very strong in Verilog or with experience in Verilog for PHY layer will be considered (and trained) if their Matlab understanding is not good.
Education Requirements:
  • B.Tech / M.Tech / MS

Job Title: Baseband Design Engineer / Baseband Sr. Design Engineer

Experience: 3 - 6 Years
Location: Hyderabad, India
Job Description :

Implement given algorithms in Matlab floating / fixed point, implement the same in Verilog (given micro-architecture design) and also verify them. Microarchitecture design tasks will be assigned based on ability, if not candidate will be trained for the same. This position is for Redpine's new chip on 802.11ax and NB-IoT (Rel 13, 14, 15) which are the very latest standards in wireless. Candidate will get a unique opportunity to associate with a world class design with lowest power consumption. He will also have a growth & huge learning opportunity on various design aspects of wireless from industry veterans.

Desired skills/background:
  • Fixed point design
  • Microarchitecture design (for physical layer)
  • Verification
  • Fluency in MATLAB and Verilog is a must. VHDL experience will also be considered. Prior experience in physical layer (digital baseband) is a must
  • Micro-architecture experience or understanding preferred but not required
Required skills/background:
  • Signal processing, Communication theory M.Tech/B.Tech level undersatnding
  • Matlab Implementation
  • Verilog (for physical layer)
Education Requirements:
  • B.Tech / M.Tech / MS from Tier-1 colleges

Job Title: VLSI Design Engineer

Experience: 2 - 4 Years
Location: Hyderabad, India
Job Description :

The position requires strong knowledge of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, interconnects, memory architecture and caches, multiple clocks and resets, high-speed interfaces, peripherals. The candidate should be able to contribute to and own multiple development stages like architecture, microarchitecture, verification of SoCs which include ARM Cortex and proprietary processor designs, AMBA AHB/AXI/APB interconnects buses, high-speed interfaces for off-chip memories and be able to deliver reusable and robust IP. The candidate should have knowledge of SoC design flows and signoff criteria including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure. Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) is part of the minimum requirements.

Minimum Qualifications:
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN and M4 processor
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
  • Knowledge of DFT including Scan, MBIST
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Knowledge of Verilog and System Verilog
  • Knowledge of scripting languages like Perl, Python, Tcl, shell
  • Good to have: Protocols knowledge : Wi-Fi, ZB, Bluetooth
Education Requirements:
B.Tech/M.Tech in ECE, EEE or CSE

Job Title: VLSI Verification Engineer

Experience: 2 - 4 Years
Location: Hyderabad, India
Job Description :

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN.

Minimum Qualifications:
  • Develop and signoff on test plans and test cases
  • Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture
  • strong knowledge of Verilog, System Verilog, UVM, C/C++
  • Experience in usage of assertions, constrained random generation, functional/code coverage
  • Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows
  • Analytical debugging skills
Preferred Qualifications:
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN
  • Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee, GPS
  • Mentoring skills
  • Exceptional problem-solving skills
  • Good written and oral communication skills
  • Good to have: Protocols knowledge : Wi-Fi, ZB, Bluetooth
Education:
B.Tech/M.Tech in ECE, EEE or CSE

Job Title: Bluetooth Developer

Experience: 3 - 8 Years
Location: Hyderabad, India
Job Description :
  • Firmware development for Bluetooth EDR and Bluetooth Low Energy protocol stack for controller or host layer features.
  • Development involving design, implementation and unit-level validation, bug fixing for new feature development.
  • System level debug of Bluetooth issues (RF, Protocol, Interoperability etc.).
  • Proactive abilities to contribute to new standards like BT 5.0.
  • Stack integration of Bluetooth or Wi-Fi on embedded Linux platform.
  • Perform design & code analysis utilizing appropriate tools.
Required Skills:
  • Hands on development in C & Embedded C
  • BT HCI layer & HCI transport development experience
  • BT EDR/LE 4.0/4.1/4.2 controller software
  • BT EDR Profiles (SPP, A2DP, AVRCP, HID, HFP etc.) experience
  • BT LE 4.0/4.1/4.2 GATT related profiles (IPSP, IPSS, PXP, HID, Heart Rate etc.)
  • Sound knowledge in BT Sniffer tools and Debugging skills
  • Good team player and problem solver
  • Ability to work in a challenging environment and deliver to commitments
  • Strong analytical skills and have good perception and anticipation
  • Must possess good verbal and written communication skills
Desired Skils:
  • Open source BT stack (BlueZ, Bluedroid etc.)
  • Bluetooth qualification experience is additional
  • Experience in L2CAP,SDAP and RFCOMM
  • Experience in LMP and Baseband
Education:
B.Tech / M.Tech

We will be glad to hear from you at hr@redpinesignals.com